The present invention generally relates to integrated circuits, and, more particularly, to a delay-locked loop (DLL).
Delay locked-loops (DLLs) are used in integrated circuits for eliminating clock skew and generating multi-phase clock signals. A DLL delays an external clock signal to generate an internal clock signal (i.e., a delayed clock signal), which is used to synchronize the operations of components within a system. The delayed clock signal has the same frequency as that of the external clock signal.
To synchronize the delayed clock signal with the external clock signal, the DLL compares a phase difference between the two and introduces a delay between them until the two clock signals are synchronized. The DLL enters a false-lock condition when a feedback loop in the DLL settles at a delay that is a multiple of 2π radians. Conventional DLLs cannot recover from this situation, and hence, may fail to achieve the desired delay of 2π radians between the delayed clock signal and the external clock signal.
A known technique to overcome the false-lock condition is to use a false-lock detection circuit that detects the false-lock condition using intermediate clock signals generated by a delay chain. The false-lock detection circuit modifies a count value for selecting an intermediate clock signal, which is then output as the delayed clock signal by the delay chain. Since this false-lock detection circuit uses multiple intermediate clock signals to detect the false-lock condition, it increases the complexity of the DLL, which increases the time taken to achieve timing sign-off. Further, the DLL performs multiple iterations to achieve a true lock, which increases the external clock signal synchronization time. In addition, the false-lock detection circuit may fail to recover from a false-lock condition caused by the loss of the clock signal and hence, an external reset signal is needed to reset the DLL in such cases.
It would be advantageous to have a DLL that detects a false-lock condition, recovers from this condition without using an external reset signal, and can quickly achieve a true lock.